SGAnalog: An End-to-End Circuit Benchmark from Open-Source Silicon Tapeouts

TEXT START: Existing analog integrated circuit design benchmarks make two questions hard to answer: whether a model has learned transferable circuit skills rather than recalled familiar examples, and whether its output works under defined process and test conditions.

The Dissection

This paper converts a formerly opaque expert craft into measurable subproblems. Its strongest contribution is not the headline score; it is the infrastructure: fixed source revisions, reproducible containers, paired schematics and netlists, training-cutoff analysis, and author testbenches.

The results expose uneven but real encroachment. Transcription remains brittle: the strongest model reaches only 56.1% exact graph isomorphism, with sharp degradation at larger scale. Sizing is more advanced: one model converges on all 17 tasks and reaches 91.2/100 against the human reference. Refusals from Claude models demonstrate that deployment policy can create a capability ceiling unrelated to technical competence.

The paper is therefore an instrument for locating the remaining human moat, not evidence that the moat is permanent.

The Core Fallacy

The central error is proxy inflation. Exact graph matching, agreement with a human sizing reference, and successful convergence are not the same thing as functional, manufacturable, autonomous circuit design. Conversely, imperfect benchmark scores do not prove that analog engineers retain durable economic protection.

The title also oversells the scope. This is an end-to-end benchmarking pipeline, not end-to-end automated tapeout. The supplied tasks do not establish autonomous specification formation, topology invention, layout, parasitic extraction, PVT and mismatch verification, DRC/LVS closure, yield optimization, lab validation, or accountability for fabricated silicon.

Under Discontinuity Thesis mechanics, however, AI does not need mystical perfection. It needs sufficiently cheap performance inside a workflow where human review, repair, and exception handling are cheaper than maintaining the old headcount. This benchmark shows that circuit knowledge can be decomposed, captured, and scored. That is the opening wound.

Hidden Assumptions

• The 273 Tiny Tapeout designs represent analog IC design broadly rather than a particular open-source subset.
• A human reference is an adequate correctness target, despite multiple valid circuit topologies and sizing tradeoffs.
• Exact graph isomorphism tracks useful engineering competence closely enough to predict production value.
• Commit dates reliably separate memorization from transferable learning.
• Author-provided testbenches adequately represent real process, reliability, yield, and fabrication constraints.
• Convergence on 17 sizing tasks generalizes beyond the selected task family.
• Model refusals can be cleanly separated from capability rather than treated as deployment constraints.
• Better performance on transcription and sizing will transfer to the integrated design loop.
• Human oversight remains economically cheap and scarce expertise remains necessary after automation absorbs the routine majority of the work.

Social Function

Primary classification: partial truth. Secondary classifications: prestige signaling and transition management.

The paper is serious measurement, not empty copium. But measurement also sanitizes the larger event. It turns the displacement of elite technical labor into a sequence of benchmark deltas, allowing institutions to discuss the collapse as an engineering roadmap rather than a labor-power problem.

Its practical function is to identify which fragments of analog expertise can be automated first, expose model weaknesses, and give developers targets for closing them. The benchmark does not defend the profession. It inventories the components from which the profession can eventually be disassembled.

The Verdict

Analog circuit design is not already dead, but its exclusivity is demonstrably artificial. Transcription and sizing can be isolated, reproduced, and attacked by models; the remaining defenses are integration, physical validation, tacit process knowledge, and liability. Those are lag defenses, not permanent laws of nature.

This paper is a narrow P1 signal, not proof of full P2 or P3. It shows the cognitive craft has become legible to automation. Once agents connect these modules to simulation, layout, verification, and fabrication feedback, the human designer’s role contracts from creator to supervisor, verifier, and exception handler. The title survives longer than the bargaining power.